This invention relates to packaging power semiconductor devices, whereby the size and weight of the package is reduced and the thermal efficiency thereof is increased.
The current trend toward very large scale integration of electronic components, greater current densities and high speed switching of power semiconductor devices has created the need to dissipate large heat build-ups. Due to higher aircraft coolant inlet temperatures specified for modern applications, prior art packaging arrangements for the purpose described have not been sufficient to enhance heat transfer characteristics essential for maintaining acceptable component temperatures, high reliability, light weight, high mean time between failures (MTBF) and lower life cycle cost.
The need for increased electrical power and improved range, particularly for military type aircraft, requires replacing prior art heavy, expensive and less efficient packaging materials and arrangements for power semiconductor devices with materials and arrangements more suitable for the intended purposes. Further, prior art packaging materials and arrangements have less than desireable heat transfer characteristics due to their relatively poor thermal conductivities. Also, mechanical failures occur as a result of mismatched thermal coefficients of expansion of the materials used.
Increased circuit density is also an important factor in designing packaging arrangements for power semiconductors. Through the use of effective packaging, circuit density is increased while package size and weight are reduced. Additionally, logic and low level analog circuitry can be cost effectively combined in the same package with the power semiconductors (chips).
The packaging arrangement for power semiconductor devices herein disclosed obviates the noted disadvantages of prior art packaging arrangements for the purposes intended, and is thus an improvement thereover.